Searched refs:mmRLC_MEM_SLP_CNTL (Results 1 – 10 of 10) sorted by relevance
| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | gfx_v9_0.c | 3573 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
3576 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
3602 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
3605 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
3831 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); in gfx_v9_0_get_clockgating_state()
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| H A D | gfx_v8_0.c | 705 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
5763 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v8_0_get_clockgating_state()
5954 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v8_0_update_medium_grain_clock_gating()
5957 WREG32(mmRLC_MEM_SLP_CNTL, data); in gfx_v8_0_update_medium_grain_clock_gating()
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_6_0_d.h | 1156 #define mmRLC_MEM_SLP_CNTL 0x30D8 macro
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| H A D | gfx_7_0_d.h | 1247 #define mmRLC_MEM_SLP_CNTL 0x30c6 macro
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| H A D | gfx_7_2_d.h | 1260 #define mmRLC_MEM_SLP_CNTL 0x30c6 macro
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| H A D | gfx_8_0_d.h | 1349 #define mmRLC_MEM_SLP_CNTL 0xec06 macro
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| H A D | gfx_8_1_d.h | 1351 #define mmRLC_MEM_SLP_CNTL 0xec06 macro
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 5907 #define mmRLC_MEM_SLP_CNTL … macro
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| H A D | gc_9_1_offset.h | 6186 #define mmRLC_MEM_SLP_CNTL … macro
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| H A D | gc_9_2_1_offset.h | 6150 #define mmRLC_MEM_SLP_CNTL … macro
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