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Searched refs:mmRLC_SRM_INDEX_CNTL_ADDR_0 (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c219 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
220 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
221 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
222 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
223 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
224 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
225 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
226 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
1996 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) in gfx_v9_1_init_rlc_save_restore_list()
H A Dgfx_v8_0.c4102 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0; in gfx_v8_0_init_save_restore_list()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_d.h1463 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 0xec8b macro
H A Dgfx_8_1_d.h1459 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 0xec8b macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6097 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 … macro
H A Dgc_9_1_offset.h6376 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 … macro
H A Dgc_9_2_1_offset.h6352 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 … macro