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Searched refs:mmRLC_SRM_INDEX_CNTL_DATA_0 (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c231 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
232 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
233 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
234 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
235 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
236 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
237 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
238 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
2000 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) in gfx_v9_1_init_rlc_save_restore_list()
H A Dgfx_v8_0.c4103 data = mmRLC_SRM_INDEX_CNTL_DATA_0; in gfx_v8_0_init_save_restore_list()
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_d.h1471 #define mmRLC_SRM_INDEX_CNTL_DATA_0 0xec93 macro
H A Dgfx_8_1_d.h1467 #define mmRLC_SRM_INDEX_CNTL_DATA_0 0xec93 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6113 #define mmRLC_SRM_INDEX_CNTL_DATA_0 … macro
H A Dgc_9_1_offset.h6392 #define mmRLC_SRM_INDEX_CNTL_DATA_0 … macro
H A Dgc_9_2_1_offset.h6368 #define mmRLC_SRM_INDEX_CNTL_DATA_0 … macro