Searched refs:mmSDMA0_CLK_CTRL (Results 1 – 10 of 10) sorted by relevance
/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | sdma_v3_0.c | 80 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 93 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 111 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 118 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 132 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 146 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 161 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 175 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, 1510 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); in sdma_v3_0_update_sdma_medium_grain_clock_gating() 1525 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); in sdma_v3_0_update_sdma_medium_grain_clock_gating() [all …]
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H A D | mxgpu_vi.c | 93 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 224 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 245 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
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H A D | sdma_v4_0.c | 62 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 107 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 122 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 1450 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); in sdma_v4_0_update_medium_grain_clock_gating() 1460 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); in sdma_v4_0_update_medium_grain_clock_gating() 1477 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); in sdma_v4_0_update_medium_grain_clock_gating() 1488 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); in sdma_v4_0_update_medium_grain_clock_gating() 1594 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); in sdma_v4_0_get_clockgating_state()
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H A D | sdma_v2_4.c | 66 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 73 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
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/dragonfly/sys/dev/drm/amd/include/asic_reg/sdma0/ |
H A D | sdma0_4_1_offset.h | 66 #define mmSDMA0_CLK_CTRL … macro
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H A D | sdma0_4_0_offset.h | 68 #define mmSDMA0_CLK_CTRL 0x001b macro
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/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/ |
H A D | oss_2_4_d.h | 160 #define mmSDMA0_CLK_CTRL 0x3403 macro
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H A D | oss_3_0_1_d.h | 157 #define mmSDMA0_CLK_CTRL 0x3403 macro
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H A D | oss_2_0_d.h | 222 #define mmSDMA0_CLK_CTRL 0x3403 macro
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H A D | oss_3_0_d.h | 294 #define mmSDMA0_CLK_CTRL 0x3403 macro
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