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Searched refs:mmSDMA0_GFX_IB_CNTL (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsdma_v3_0.c81 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
100 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
119 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
133 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
147 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
167 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
523 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop()
525 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v3_0_gfx_stop()
735 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_resume()
741 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v3_0_gfx_resume()
H A Dmxgpu_vi.c107 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
246 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
H A Dsdma_v4_0.c63 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
108 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
509 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v4_0_gfx_stop()
511 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v4_0_gfx_stop()
723 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v4_0_gfx_resume()
729 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v4_0_gfx_resume()
H A Dsdma_v2_4.c348 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop()
350 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v2_4_gfx_stop()
466 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_resume()
472 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v2_4_gfx_resume()
/dragonfly/sys/dev/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h224 #define mmSDMA0_GFX_IB_CNTL … macro
H A Dsdma0_4_0_offset.h228 #define mmSDMA0_GFX_IB_CNTL 0x008a macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h197 #define mmSDMA0_GFX_IB_CNTL 0x348a macro
H A Doss_3_0_1_d.h224 #define mmSDMA0_GFX_IB_CNTL 0x348a macro
H A Doss_2_0_d.h256 #define mmSDMA0_GFX_IB_CNTL 0x348a macro
H A Doss_3_0_d.h349 #define mmSDMA0_GFX_IB_CNTL 0x348a macro