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Searched refs:mmSDMA0_GFX_MIDCMD_DATA5 (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h280 #define mmSDMA0_GFX_MIDCMD_DATA5 … macro
H A Dsdma0_4_0_offset.h284 #define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/
H A Doss_3_0_1_d.h248 #define mmSDMA0_GFX_MIDCMD_DATA5 0x34c6 macro
H A Doss_3_0_d.h373 #define mmSDMA0_GFX_MIDCMD_DATA5 0x34c6 macro