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Searched refs:mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h264 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO … macro
H A Dsdma0_4_0_offset.h268 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h194 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 macro
H A Doss_3_0_1_d.h221 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 macro
H A Doss_2_0_d.h253 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 macro
H A Doss_3_0_d.h346 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x3487 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsdma_v3_0.c713 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], in sdma_v3_0_gfx_resume()
H A Dsdma_v4_0.c708 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), in sdma_v4_0_gfx_resume()