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Searched refs:mmSDMA0_RLC0_MIDCMD_DATA0 (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h354 #define mmSDMA0_RLC0_MIDCMD_DATA0 … macro
H A Dsdma0_4_0_offset.h442 #define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/
H A Doss_3_0_1_d.h281 #define mmSDMA0_RLC0_MIDCMD_DATA0 0x3541 macro
H A Doss_3_0_d.h403 #define mmSDMA0_RLC0_MIDCMD_DATA0 0x3541 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v8.c512 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL; in kgd_hqd_sdma_dump()
H A Damdgpu_amdkfd_gfx_v9.c622 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; in kgd_hqd_sdma_dump()