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Searched refs:mmSDMA0_RLC0_RB_WPTR_HI (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h302 #define mmSDMA0_RLC0_RB_WPTR_HI … macro
H A Dsdma0_4_0_offset.h390 #define mmSDMA0_RLC0_RB_WPTR_HI 0x0146 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v9.c576 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, in kgd_hqd_sdma_load()
581 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, in kgd_hqd_sdma_load()