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Searched refs:mmSDMA1_RLC0_IB_CNTL (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dmxgpu_vi.c112 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
252 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
H A Dsdma_v3_0.c87 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
105 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
125 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
139 mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
155 mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
H A Dsdma_v4_0.c80 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h333 #define mmSDMA1_RLC0_IB_CNTL 0x370a macro
H A Doss_3_0_1_d.h434 #define mmSDMA1_RLC0_IB_CNTL 0x370a macro
H A Doss_2_0_d.h369 #define mmSDMA1_RLC0_IB_CNTL 0x370a macro
H A Doss_3_0_d.h535 #define mmSDMA1_RLC0_IB_CNTL 0x370a macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_offset.h390 #define mmSDMA1_RLC0_IB_CNTL 0x014a macro