Searched refs:mmSDMA1_RLC0_RB_WPTR_POLL_CNTL (Results 1 – 6 of 6) sorted by relevance
| /dragonfly/sys/dev/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 328 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 macro
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| H A D | oss_3_0_1_d.h | 429 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 macro
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| H A D | oss_2_0_d.h | 364 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 macro
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| H A D | oss_3_0_d.h | 530 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x3705 macro
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/sdma1/ |
| H A D | sdma1_4_0_offset.h | 384 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147 macro
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | sdma_v4_0.c | 81 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
136 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
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