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Searched refs:mmSMU_INTERRUPT_CONTROL (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_d.h1020 #define mmSMU_INTERRUPT_CONTROL 0x12e macro
H A Ddce_10_0_d.h1177 #define mmSMU_INTERRUPT_CONTROL 0x12e macro
H A Ddce_11_0_d.h986 #define mmSMU_INTERRUPT_CONTROL 0x12e macro
H A Ddce_11_2_d.h1057 #define mmSMU_INTERRUPT_CONTROL 0x12e macro
H A Ddce_12_0_offset.h736 #define mmSMU_INTERRUPT_CONTROL … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h934 #define mmSMU_INTERRUPT_CONTROL … macro