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Searched refs:mmSPI_CDBG_SYS_CS0_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2630 #define mmSPI_CDBG_SYS_CS0_BASE_IDX macro
H A Dgc_9_2_1_offset.h2873 #define mmSPI_CDBG_SYS_CS0_BASE_IDX macro