Searched refs:mmUVD_JRBC_RB_WPTR (Results 1 – 3 of 3) sorted by relevance
| /dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_7_0_offset.h | 126 #define mmUVD_JRBC_RB_WPTR … macro
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 240 #define mmUVD_JRBC_RB_WPTR … macro
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | vcn_v1_0.c | 785 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0); in vcn_v1_0_start()
789 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); in vcn_v1_0_start()
1218 return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); in vcn_v1_0_jpeg_ring_get_wptr()
1232 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_jpeg_ring_set_wptr()
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