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Searched refs:mmUVD_JRBC_STATUS (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h264 #define mmUVD_JRBC_STATUS … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvcn_v1_0.c1396 PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); in vcn_v1_0_jpeg_ring_emit_ib()