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Searched refs:mmUVD_LMI_SWAP_CNTL (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h51 #define mmUVD_LMI_SWAP_CNTL 0x3D6D macro
H A Duvd_4_2_d.h51 #define mmUVD_LMI_SWAP_CNTL 0x3d6d macro
H A Duvd_5_0_d.h57 #define mmUVD_LMI_SWAP_CNTL 0x3d6d macro
H A Duvd_6_0_d.h73 #define mmUVD_LMI_SWAP_CNTL 0x3d6d macro
H A Duvd_7_0_offset.h160 #define mmUVD_LMI_SWAP_CNTL … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h318 #define mmUVD_LMI_SWAP_CNTL … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Duvd_v5_0.c339 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in uvd_v5_0_start()
H A Duvd_v6_0.c768 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in uvd_v6_0_start()
H A Dvcn_v1_0.c669 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in vcn_v1_0_start()
H A Duvd_v7_0.c998 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); in uvd_v7_0_start()