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Searched refs:mmUVD_MASTINT_EN (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h52 #define mmUVD_MASTINT_EN 0x3D40 macro
H A Duvd_4_2_d.h47 #define mmUVD_MASTINT_EN 0x3d40 macro
H A Duvd_5_0_d.h53 #define mmUVD_MASTINT_EN 0x3d40 macro
H A Duvd_6_0_d.h69 #define mmUVD_MASTINT_EN 0x3d40 macro
H A Duvd_7_0_offset.h152 #define mmUVD_MASTINT_EN … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h308 #define mmUVD_MASTINT_EN … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Duvd_v5_0.c312 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v5_0_start()
389 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); in uvd_v5_0_start()
H A Duvd_v7_0.c850 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in uvd_v7_0_sriov_start()
887 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in uvd_v7_0_sriov_start()
963 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, in uvd_v7_0_start()
1054 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), in uvd_v7_0_start()
H A Dvcn_v1_0.c635 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, in vcn_v1_0_start()
724 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), in vcn_v1_0_start()
H A Duvd_v6_0.c818 WREG32_P(mmUVD_MASTINT_EN, in uvd_v6_0_start()