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Searched refs:mmUVD_NO_OP (Results 1 – 12 of 12) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h61 #define mmUVD_NO_OP 0x3BFF macro
H A Duvd_4_2_d.h37 #define mmUVD_NO_OP 0x3bff macro
H A Duvd_5_0_d.h37 #define mmUVD_NO_OP 0x3bff macro
H A Duvd_6_0_d.h38 #define mmUVD_NO_OP 0x3bff macro
H A Duvd_7_0_offset.h80 #define mmUVD_NO_OP … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h146 #define mmUVD_NO_OP … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Duvd_v5_0.c556 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); in uvd_v5_0_ring_insert_nop()
H A Damdgpu_vcn.c309 ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0); in amdgpu_vcn_dec_send_msg()
H A Damdgpu_uvd.c916 case mmUVD_NO_OP: in amdgpu_uvd_cs_reg()
H A Duvd_v6_0.c1096 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); in uvd_v6_0_ring_insert_nop()
H A Dvcn_v1_0.c1613 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); in vcn_v1_0_dec_ring_insert_nop()
H A Duvd_v7_0.c1395 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0)); in uvd_v7_0_ring_insert_nop()