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Searched refs:mmUVD_PGFSM_CONFIG (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h62 #define mmUVD_PGFSM_CONFIG 0x38F8 macro
H A Duvd_4_2_d.h88 #define mmUVD_PGFSM_CONFIG 0x38f8 macro
H A Duvd_5_0_d.h100 #define mmUVD_PGFSM_CONFIG 0x38c0 macro
H A Duvd_6_0_d.h116 #define mmUVD_PGFSM_CONFIG 0x38c0 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h28 #define mmUVD_PGFSM_CONFIG … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvcn_v1_0.c541 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_1_0_disable_static_power_gating()
555 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_1_0_disable_static_power_gating()
594 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_1_0_enable_static_power_gating()