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Searched refs:mmUVD_RB_WPTR (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_d.h48 #define mmUVD_RB_WPTR 0x3c2a macro
H A Duvd_7_0_offset.h102 #define mmUVD_RB_WPTR … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h202 #define mmUVD_RB_WPTR … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Duvd_v6_0.c126 return RREG32(mmUVD_RB_WPTR); in uvd_v6_0_enc_ring_get_wptr()
157 WREG32(mmUVD_RB_WPTR, in uvd_v6_0_enc_ring_set_wptr()
858 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
H A Dvcn_v1_0.c767 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start()
1095 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); in vcn_v1_0_enc_ring_get_wptr()
1112 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, in vcn_v1_0_enc_ring_set_wptr()
H A Duvd_v7_0.c124 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); in uvd_v7_0_enc_ring_get_wptr()
162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, in uvd_v7_0_enc_ring_set_wptr()
1097 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_start()