Searched refs:mmUVD_VCPU_CACHE_OFFSET1 (Results 1 – 10 of 10) sorted by relevance
| /dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_0_d.h | 89 #define mmUVD_VCPU_CACHE_OFFSET1 0x3D38 macro
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| H A D | uvd_4_2_d.h | 62 #define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 macro
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| H A D | uvd_5_0_d.h | 68 #define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 macro
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| H A D | uvd_6_0_d.h | 84 #define mmUVD_VCPU_CACHE_OFFSET1 0x3d84 macro
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| H A D | uvd_7_0_offset.h | 180 #define mmUVD_VCPU_CACHE_OFFSET1 … macro
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| /dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 342 #define mmUVD_VCPU_CACHE_OFFSET1 … macro
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | uvd_v5_0.c | 273 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); in uvd_v5_0_mc_resume()
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| H A D | uvd_v7_0.c | 692 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21)); in uvd_v7_0_mc_resume()
831 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21)); in uvd_v7_0_sriov_start()
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| H A D | uvd_v6_0.c | 612 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); in uvd_v6_0_mc_resume()
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| H A D | vcn_v1_0.c | 304 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v1_0_mc_resume()
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