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Searched refs:mmUVD_VCPU_CACHE_SIZE2_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_offset.h187 #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h349 #define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX … macro