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Searched refs:mmUVD_VCPU_CNTL (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h94 #define mmUVD_VCPU_CNTL 0x3D98 macro
H A Duvd_4_2_d.h66 #define mmUVD_VCPU_CNTL 0x3d98 macro
H A Duvd_5_0_d.h72 #define mmUVD_VCPU_CNTL 0x3d98 macro
H A Duvd_6_0_d.h88 #define mmUVD_VCPU_CNTL 0x3d98 macro
H A Duvd_7_0_offset.h188 #define mmUVD_VCPU_CNTL … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h350 #define mmUVD_VCPU_CNTL … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Duvd_v5_0.c354 WREG32(mmUVD_VCPU_CNTL, 1 << 9); in uvd_v5_0_start()
449 WREG32(mmUVD_VCPU_CNTL, 0x0); in uvd_v5_0_stop()
H A Duvd_v7_0.c883 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), in uvd_v7_0_sriov_start()
1014 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL, in uvd_v7_0_start()
1141 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0); in uvd_v7_0_stop()
H A Duvd_v6_0.c783 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v6_0_start()
895 WREG32(mmUVD_VCPU_CNTL, 0x0); in uvd_v6_0_stop()
H A Dvcn_v1_0.c684 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, in vcn_v1_0_start()
822 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0); in vcn_v1_0_stop()