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Searched refs:mmVCE_LMI_SWAP_CNTL1 (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_d.h34 #define mmVCE_LMI_SWAP_CNTL1 0x83AE macro
H A Dvce_2_0_d.h63 #define mmVCE_LMI_SWAP_CNTL1 0x852e macro
H A Dvce_3_0_d.h68 #define mmVCE_LMI_SWAP_CNTL1 0x85ae macro
H A Dvce_4_0_offset.h140 #define mmVCE_LMI_SWAP_CNTL1 … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v4_0.c244 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0); in vce_v4_0_sriov_start()
613 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0); in vce_v4_0_mc_resume()
H A Dvce_v3_0.c542 WREG32(mmVCE_LMI_SWAP_CNTL1, 0); in vce_v3_0_mc_resume()