Home
last modified time | relevance | path

Searched refs:mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/vce/
H A Dvce_4_0_offset.h162 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v4_0.c249 mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), in vce_v4_0_sriov_start()
256 mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), in vce_v4_0_sriov_start()
617 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), in vce_v4_0_mc_resume()
622 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), in vce_v4_0_mc_resume()
H A Dvce_v3_0.c49 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616 macro
547 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()