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Searched refs:mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/vce/
H A Dvce_4_0_offset.h164 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v3_0.c50 #define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617 macro
548 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
H A Dvce_v4_0.c263 mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), in vce_v4_0_sriov_start()
633 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), (adev->vce.gpu_addr >> 8)); in vce_v4_0_mc_resume()