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Searched refs:mmVCE_MMSCH_VF_MAILBOX_HOST (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/vce/
H A Dvce_4_0_offset.h196 #define mmVCE_MMSCH_VF_MAILBOX_HOST … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v4_0.c184 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001); in vce_v4_0_mmsch_start()
H A Duvd_v7_0.c750 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001); in uvd_v7_0_mmsch_start()