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Searched refs:mmVCE_RB_BASE_HI (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_d.h38 #define mmVCE_RB_BASE_HI 0x8061 macro
H A Dvce_2_0_d.h42 #define mmVCE_RB_BASE_HI 0x8061 macro
H A Dvce_3_0_d.h42 #define mmVCE_RB_BASE_HI 0x8061 macro
H A Dvce_4_0_offset.h82 #define mmVCE_RB_BASE_HI … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v4_0.c235 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), in vce_v4_0_sriov_start()
340 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); in vce_v4_0_start()
H A Dvce_v3_0.c285 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()