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Searched refs:mmVCE_RB_BASE_HI3 (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/vce/
H A Dvce_3_0_d.h50 #define mmVCE_RB_BASE_HI3 0x80d5 macro
H A Dvce_4_0_offset.h98 #define mmVCE_RB_BASE_HI3 … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v3_0.c299 WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
H A Dvce_v4_0.c356 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI3), upper_32_bits(ring->gpu_addr)); in vce_v4_0_start()