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Searched refs:mmVCE_RB_BASE_LO (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_d.h40 #define mmVCE_RB_BASE_LO 0x8060 macro
H A Dvce_2_0_d.h41 #define mmVCE_RB_BASE_LO 0x8060 macro
H A Dvce_3_0_d.h41 #define mmVCE_RB_BASE_LO 0x8060 macro
H A Dvce_4_0_offset.h80 #define mmVCE_RB_BASE_LO … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v4_0.c233 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), in vce_v4_0_sriov_start()
339 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), ring->gpu_addr); in vce_v4_0_start()
H A Dvce_v3_0.c284 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); in vce_v3_0_start()