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Searched refs:mmVCE_RB_WPTR2 (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_d.h47 #define mmVCE_RB_WPTR2 0x805F macro
H A Dvce_2_0_d.h40 #define mmVCE_RB_WPTR2 0x805f macro
H A Dvce_3_0_d.h40 #define mmVCE_RB_WPTR2 0x805f macro
H A Dvce_4_0_offset.h78 #define mmVCE_RB_WPTR2 … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v3_0.c125 v = RREG32(mmVCE_RB_WPTR2); in vce_v3_0_ring_get_wptr()
156 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
290 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_start()
H A Dvce_v4_0.c90 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2)); in vce_v4_0_ring_get_wptr()
117 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), in vce_v4_0_ring_set_wptr()
346 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr)); in vce_v4_0_start()