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Searched refs:mmVCE_UENC_CLOCK_GATING_2 (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/vce/
H A Dvce_3_0_d.h57 #define mmVCE_UENC_CLOCK_GATING_2 0x8210 macro
H A Dvce_4_0_offset.h120 #define mmVCE_UENC_CLOCK_GATING_2 … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v3_0.c193 data = RREG32(mmVCE_UENC_CLOCK_GATING_2); in vce_v3_0_set_vce_sw_clock_gating()
196 WREG32(mmVCE_UENC_CLOCK_GATING_2, data); in vce_v3_0_set_vce_sw_clock_gating()
218 data = RREG32(mmVCE_UENC_CLOCK_GATING_2); in vce_v3_0_set_vce_sw_clock_gating()
220 WREG32(mmVCE_UENC_CLOCK_GATING_2, data); in vce_v3_0_set_vce_sw_clock_gating()
H A Dvce_v4_0.c825 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2));
828 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data);
850 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2));
852 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data);