Home
last modified time | relevance | path

Searched refs:mmVCE_VCPU_CACHE_OFFSET2 (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_d.h58 #define mmVCE_VCPU_CACHE_OFFSET2 0x800D macro
H A Dvce_2_0_d.h33 #define mmVCE_VCPU_CACHE_OFFSET2 0x800d macro
H A Dvce_3_0_d.h33 #define mmVCE_VCPU_CACHE_OFFSET2 0x800d macro
H A Dvce_4_0_offset.h40 #define mmVCE_VCPU_CACHE_OFFSET2 … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v3_0.c564 WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); in vce_v3_0_mc_resume()
573 WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff); in vce_v3_0_mc_resume()
H A Dvce_v4_0.c289 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), in vce_v4_0_sriov_start()
644 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), (offset & ~0x0f000000) | (2 << 24)); in vce_v4_0_mc_resume()