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Searched refs:mmVCE_VCPU_CACHE_SIZE2 (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_d.h61 #define mmVCE_VCPU_CACHE_SIZE2 0x800E macro
H A Dvce_2_0_d.h34 #define mmVCE_VCPU_CACHE_SIZE2 0x800e macro
H A Dvce_3_0_d.h34 #define mmVCE_VCPU_CACHE_SIZE2 0x800e macro
H A Dvce_4_0_offset.h42 #define mmVCE_VCPU_CACHE_SIZE2 … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v3_0.c565 WREG32(mmVCE_VCPU_CACHE_SIZE2, size); in vce_v3_0_mc_resume()
574 WREG32(mmVCE_VCPU_CACHE_SIZE2, size); in vce_v3_0_mc_resume()
H A Dvce_v4_0.c291 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size); in vce_v4_0_sriov_start()
645 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size); in vce_v4_0_mc_resume()