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Searched refs:mmVCE_VCPU_CNTL (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_d.h62 #define mmVCE_VCPU_CNTL 0x8005 macro
H A Dvce_2_0_d.h28 #define mmVCE_VCPU_CNTL 0x8005 macro
H A Dvce_3_0_d.h28 #define mmVCE_VCPU_CNTL 0x8005 macro
H A Dvce_4_0_offset.h30 #define mmVCE_VCPU_CNTL … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvce_v3_0.c307 WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001); in vce_v3_0_start()
344 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001); in vce_v3_0_stop()
544 WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000); in vce_v3_0_mc_resume()
H A Dvce_v4_0.c301 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), in vce_v4_0_sriov_start()
363 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001); in vce_v4_0_start()
385 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001); in vce_v4_0_stop()