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Searched refs:mmWD_CNTL_SB_BUF_BASE_HI (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h4893 #define mmWD_CNTL_SB_BUF_BASE_HI … macro
H A Dgc_9_1_offset.h5180 #define mmWD_CNTL_SB_BUF_BASE_HI … macro
H A Dgc_9_2_1_offset.h5136 #define mmWD_CNTL_SB_BUF_BASE_HI … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v9_0.c1412 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data); in gfx_v9_0_ngg_en()