Searched refs:mmio (Results 1 – 3 of 3) sorted by relevance
159 struct intel_vgpu_mmio mmio; member237 void *mmio; member265 struct intel_gvt_mmio mmio; member381 (*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))383 (*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))385 (*(u16 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))387 (*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))389 (*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))391 (*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))393 (*(u16 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))[all …]
398 i915_reg_t mmio; in intel_ring_setup_status_page() local412 mmio = RENDER_HWS_PGA_GEN7; in intel_ring_setup_status_page()415 mmio = BLT_HWS_PGA_GEN7; in intel_ring_setup_status_page()418 mmio = BSD_HWS_PGA_GEN7; in intel_ring_setup_status_page()421 mmio = VEBOX_HWS_PGA_GEN7; in intel_ring_setup_status_page()425 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); in intel_ring_setup_status_page()428 mmio = RING_HWS_PGA(engine->mmio_base); in intel_ring_setup_status_page()434 I915_WRITE(mmio, engine->status_page.ggtt_offset); in intel_ring_setup_status_page()435 POSTING_READ(mmio); in intel_ring_setup_status_page()
1439 u32 mmio = flex_mmio[i];1452 if (i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) {1459 reg_state[state_offset] = mmio;1497 u32 mmio = flex_mmio[i];1511 if (i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) {1518 *cs++ = mmio;