/dragonfly/sys/dev/powermng/coretemp/ |
H A D | coretemp.c | 230 uint64_t msr; in coretemp_attach() local 256 msr = rdmsr(MSR_BIOS_SIGN); in coretemp_attach() 257 msr = msr >> 32; in coretemp_attach() 258 if (msr < 0x39) { in coretemp_attach() 279 msr = rdmsr(MSR_IA32_EXT_CONFIG); in coretemp_attach() 280 if (msr & (1 << 30)) in coretemp_attach() 308 tjtarget = (msr >> 16) & 0xff; in coretemp_attach() 599 *msr = rdmsr(MSR_THERM_STATUS); in coretemp_msr_fetch() 647 uint64_t msr; in coretemp_sensor_task() local 651 temp = coretemp_msr_temp(sc, msr); in coretemp_sensor_task() [all …]
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/dragonfly/sys/platform/pc64/x86_64/ |
H A D | amd64_mem.c | 177 int i, j, msr; in amd64_mrfetch() local 185 msrv = rdmsr(msr); in amd64_mrfetch() 197 msrv = rdmsr(msr); in amd64_mrfetch() 209 msrv = rdmsr(msr); in amd64_mrfetch() 224 msrv = rdmsr(msr); in amd64_mrfetch() 303 int i, j, msr; in amd64_mrstoreone() local 336 wrmsr(msr, msrv); in amd64_mrstoreone() 348 wrmsr(msr, msrv); in amd64_mrstoreone() 360 wrmsr(msr, msrv); in amd64_mrstoreone() 369 omsrv = rdmsr(msr); in amd64_mrstoreone() [all …]
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H A D | initcpu.c | 211 uint64_t msr; in initializecpu() local 260 if ((msr & 1) == 0) { in initializecpu() 264 msr |= 1; in initializecpu() 278 msr = rdmsr(0xc001001f); in initializecpu() 279 msr |= (uint64_t)1 << 54; in initializecpu() 280 wrmsr(0xc001001f, msr); in initializecpu() 294 msr = rdmsr(0xc001102a); in initializecpu() 296 wrmsr(0xc001102a, msr); in initializecpu() 310 msr = rdmsr(0xc0011020); in initializecpu() 312 wrmsr(0xc0011020, msr); in initializecpu() [all …]
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H A D | vm_machdep.c | 886 uint64_t msr; in mds_check_support() local 908 msr = 0; in mds_check_support() 909 if (rdmsr_safe(MSR_IA32_ARCH_CAPABILITIES, &msr)) { in mds_check_support() 913 if (msr & IA32_ARCH_CAP_MDS_NO) in mds_check_support()
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H A D | mp_machdep.c | 250 u_int64_t msr, cr0; in init_secondary() local 338 msr = rdmsr(MSR_EFER) | EFER_SCE; in init_secondary() 339 wrmsr(MSR_EFER, msr); in init_secondary() 342 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | in init_secondary() 344 wrmsr(MSR_STAR, msr); in init_secondary()
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/dragonfly/sys/dev/powermng/corepower/ |
H A D | corepower.c | 56 u_int msr; member 91 char *desc, u_int msr, int cpu); 94 static int corepower_try(u_int msr, char *name); 386 corepower_sens_init(struct corepower_sensor *sens, char *desc, u_int msr, in corepower_sens_init() argument 392 sens->msr = msr; in corepower_sens_init() 393 sens->energy = rdmsr(sens->msr) & 0xffffffffU; in corepower_sens_init() 402 a = rdmsr(sens->msr) & 0xffffffffU; in corepower_sens_update() 413 corepower_try(u_int msr, char *name) in corepower_try() argument 417 if (rdmsr_safe(msr, &val) != 0) { in corepower_try() 418 kprintf("msr %s (0x%08x) not available\n", name, msr); in corepower_try()
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/dragonfly/sys/bus/u4b/net/ |
H A D | ruephy.c | 196 int bmsr, bmcr, msr; in ruephy_status() local 201 msr = PHY_READ(phy, RUEPHY_MII_MSR) | PHY_READ(phy, RUEPHY_MII_MSR); in ruephy_status() 202 if (msr & RUEPHY_MSR_LINK) in ruephy_status() 220 if (msr & RUEPHY_MSR_SPEED100) in ruephy_status() 225 if (msr & RUEPHY_MSR_DUPLEX) in ruephy_status()
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/dragonfly/sys/dev/virtual/nvmm/x86/ |
H A D | nvmm_x86_vmx.c | 647 uint32_t msr; member 912 uint64_t msr; in vmx_get_revision() local 917 return msr; in vmx_get_revision() 2473 if (msr < 0x00002000) { in vmx_vcpu_msr_allow() 2476 } else if (msr >= 0xC0000000 && msr < 0xC0002000) { in vmx_vcpu_msr_allow() 2483 bitoff = (msr & 0x7); in vmx_vcpu_msr_allow() 3338 uint64_t msr; in vmx_ident() local 3450 if (!(msr & IA32_VMX_EPT_VPID_UC) && !(msr & IA32_VMX_EPT_VPID_WB)) { in vmx_ident() 3477 uint64_t msr, cr4; in OS_IPI_FUNC() local 3510 uint64_t msr; in vmx_init_l1tf() local [all …]
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H A D | nvmm_x86_svmfunc.S | 65 #define HOST_SAVE_MSR(msr) \ argument 66 movq $msr,%rcx ;\ 71 #define HOST_RESTORE_MSR(msr) \ argument 74 movq $msr,%rcx ;\
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H A D | nvmm_x86_svm.c | 1736 if (msr < 0x00002000) { in svm_vcpu_msr_allow() 1739 } else if (msr >= 0xC0000000 && msr < 0xC0002000) { in svm_vcpu_msr_allow() 1742 } else if (msr >= 0xC0010000 && msr < 0xC0012000) { in svm_vcpu_msr_allow() 2482 uint64_t msr; in svm_ident() local 2527 msr = rdmsr(MSR_VM_CR); in svm_ident() 2528 if ((msr & VM_CR_SVMED) && (msr & VM_CR_LOCK)) { in svm_ident() 2563 uint64_t msr; in OS_IPI_FUNC() local 2574 msr = rdmsr(MSR_EFER); in OS_IPI_FUNC() 2576 msr |= EFER_SVME; in OS_IPI_FUNC() 2578 msr &= ~EFER_SVME; in OS_IPI_FUNC() [all …]
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/dragonfly/sys/platform/pc64/apic/ |
H A D | lapic.h | 106 #define LAPIC_MSR_READ(msr) rdmsr((msr)) argument 107 #define LAPIC_MSR_WRITE(msr, val) wrmsr((msr), (val)) argument
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H A D | lapic.c | 797 uint64_t msr; in lapic_timer_fixup_handler() local 799 msr = rdmsr(0xc0010055); in lapic_timer_fixup_handler() 800 if (msr & 0x18000000) { in lapic_timer_fixup_handler() 805 wrmsr(0xc0010055, msr & ~0x18000000ULL); in lapic_timer_fixup_handler()
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/dragonfly/sys/dev/netif/mii_layer/ |
H A D | ruephy.c | 249 int bmsr, bmcr, msr; in ruephy_status() local 254 msr = PHY_READ(sc, RUEPHY_MII_MSR) | PHY_READ(sc, RUEPHY_MII_MSR); in ruephy_status() 255 if (msr & RUEPHY_MSR_LINK) in ruephy_status() 274 if (msr & RUEPHY_MSR_SPEED100) in ruephy_status() 279 if (msr & RUEPHY_MSR_DUPLEX) in ruephy_status()
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/dragonfly/sys/bus/u4b/serial/ |
H A D | uftdi.c | 433 uint8_t msr; in uftdi_read_callback() local 451 msr = 0; in uftdi_read_callback() 453 msr |= SER_CTS; in uftdi_read_callback() 455 msr |= SER_DSR; in uftdi_read_callback() 457 msr |= SER_RI; in uftdi_read_callback() 459 msr |= SER_DCD; in uftdi_read_callback() 461 if ((sc->sc_msr != msr) || in uftdi_read_callback() 464 "lsr=0x%02x (0x%02x)\n", msr, sc->sc_msr, in uftdi_read_callback() 467 sc->sc_msr = msr; in uftdi_read_callback() 706 uftdi_cfg_get_status(struct ucom_softc *ucom, uint8_t *lsr, uint8_t *msr) in uftdi_cfg_get_status() argument [all …]
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H A D | uslcom.c | 586 uslcom_get_status(struct ucom_softc *ucom, uint8_t *lsr, uint8_t *msr) in uslcom_get_status() argument 593 *msr = sc->sc_msr; in uslcom_get_status() 732 uint8_t msr = 0; in uslcom_control_callback() local 740 msr |= SER_CTS; in uslcom_control_callback() 742 msr |= SER_DSR; in uslcom_control_callback() 744 msr |= SER_RI; in uslcom_control_callback() 746 msr |= SER_DCD; in uslcom_control_callback() 748 if (msr != sc->sc_msr) { in uslcom_control_callback() 750 "(was 0x%02x)\n", msr, sc->sc_msr); in uslcom_control_callback() 751 sc->sc_msr = msr; in uslcom_control_callback()
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H A D | umoscom.c | 500 uint8_t msr; in umoscom_cfg_get_status() local 507 msr = umoscom_cfg_read(sc, UMOSCOM_MSR); in umoscom_cfg_get_status() 511 if (msr & UMOSCOM_MSR_CTS) in umoscom_cfg_get_status() 514 if (msr & UMOSCOM_MSR_CD) in umoscom_cfg_get_status() 517 if (msr & UMOSCOM_MSR_RI) in umoscom_cfg_get_status() 520 if (msr & UMOSCOM_MSR_RTS) in umoscom_cfg_get_status()
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H A D | uark.c | 399 uark_cfg_get_status(struct ucom_softc *ucom, uint8_t *lsr, uint8_t *msr) in uark_cfg_get_status() argument 404 *msr = sc->sc_msr; in uark_cfg_get_status()
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/dragonfly/sys/dev/misc/cpuctl/ |
H A D | cpuctl.c | 192 data->msr, cpu); in cpuctl_do_msr() 197 ret = rdmsr_safe(data->msr, &data->data); in cpuctl_do_msr() 199 ret = wrmsr_safe(data->msr, data->data); in cpuctl_do_msr() 202 ret = rdmsr_safe(data->msr, ®); in cpuctl_do_msr() 204 ret = wrmsr_safe(data->msr, reg | data->data); in cpuctl_do_msr() 208 ret = rdmsr_safe(data->msr, ®); in cpuctl_do_msr() 210 ret = wrmsr_safe(data->msr, reg & ~data->data); in cpuctl_do_msr()
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/dragonfly/usr.sbin/cpucontrol/ |
H A D | cpucontrol.c | 225 unsigned int msr; in do_msr() local 248 msr = strtoul(cmdarg, &endptr, 16); in do_msr() 293 args.msr = msr; in do_msr() 331 fprintf(stdout, "MSR 0x%x: 0x%.8x 0x%.8x\n", msr, in do_msr()
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H A D | via.c | 93 .msr = MSR_IA32_PLATFORM_ID, in via_update() 127 msrargs.msr = MSR_BIOS_SIGN; in via_update()
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H A D | intel.c | 98 .msr = MSR_IA32_PLATFORM_ID, in intel_update() 134 msrargs.msr = MSR_BIOS_SIGN; in intel_update()
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H A D | amd10h.c | 132 msrargs.msr = 0x0000008b; in amd10h_update() 289 msrargs.msr = 0x0000008b; in amd10h_update()
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/dragonfly/sys/cpu/x86_64/include/ |
H A D | cpufunc.h | 525 rdmsr(u_int msr) in rdmsr() argument 529 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr)); in rdmsr() 591 wrmsr(u_int msr, u_int64_t newval) in wrmsr() argument 599 : "a" (low), "d" (high), "c" (msr) in wrmsr() 969 u_int64_t rdmsr(u_int msr); 975 void wrmsr(u_int msr, u_int64_t newval); 997 int rdmsr_safe(u_int msr, uint64_t *val); 998 int wrmsr_safe(u_int msr, uint64_t newval);
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/dragonfly/sys/platform/pc64/acpica/ |
H A D | acpi_pstate_machdep.c | 217 uint32_t msr; in acpi_pst_amd1x_check_pstates1() local 219 msr = msr_start + in acpi_pst_amd1x_check_pstates1() 221 if (msr >= msr_end) { in acpi_pst_amd1x_check_pstates1() 223 "does not exist\n", mycpuid, msr); in acpi_pst_amd1x_check_pstates1() 227 pstate = rdmsr(msr); in acpi_pst_amd1x_check_pstates1() 230 "is not enabled\n", mycpuid, msr); in acpi_pst_amd1x_check_pstates1()
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/dragonfly/sys/sys/ |
H A D | cpuctl.h | 36 int msr; /* MSR to read */ member
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