Searched refs:mvdd_dependency_on_mclk (Results 1 – 10 of 10) sorted by relevance
1242 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; in init_clock_voltage_dependency()1377 &hwmgr->dyn_state.mvdd_dependency_on_mclk, table); in init_clock_voltage_dependency()1683 kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk); in pp_tables_uninitialize()1684 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; in pp_tables_uninitialize()
269 hwmgr->dyn_state.mvdd_dependency_on_mclk); in smu7_construct_voltage_tables()735 allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
197 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; member
423 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in amdgpu_parse_extended_power_table()782 kfree(dyn_state->mvdd_dependency_on_mclk.entries); in amdgpu_free_extended_power_table()
1201 if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) { in ci_populate_single_memory_level()1203 hwmgr->dyn_state.mvdd_dependency_on_mclk, in ci_populate_single_memory_level()1356 for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) { in ci_populate_mvdd_value()1357 if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) { in ci_populate_mvdd_value()1364 PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count, in ci_populate_mvdd_value()
1403 for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) { in iceland_populate_mvdd_value()1404 if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) { in iceland_populate_mvdd_value()1411 PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count, in iceland_populate_mvdd_value()
597 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk; member
959 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in r600_parse_extended_power_table()1306 kfree(dyn_state->mvdd_dependency_on_mclk.entries); in r600_free_extended_power_table()
2217 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_construct_voltage_tables()2348 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { in ci_populate_mvdd_value()2349 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { in ci_populate_mvdd_value()2355 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) in ci_populate_mvdd_value()2933 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { in ci_populate_single_memory_level()2935 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_populate_single_memory_level()3558 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; in ci_setup_default_dpm_tables()
1487 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; member