| /dragonfly/sys/dev/drm/radeon/ |
| H A D | rs780_dpm.c | 426 struct radeon_ps *new_ps, in rs780_set_engine_clock_scaling() argument
474 struct radeon_ps *new_ps, in rs780_set_engine_clock_spc() argument
493 struct radeon_ps *new_ps, in rs780_activate_engine_clk_scaling() argument
523 struct radeon_ps *new_ps) in rs780_enable_voltage_scaling() argument
564 struct radeon_ps *new_ps, in rs780_set_uvd_clock_before_set_eng_clock() argument
570 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_before_set_eng_clock()
571 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
581 struct radeon_ps *new_ps, in rs780_set_uvd_clock_after_set_eng_clock() argument
588 (new_ps->dclk == old_ps->dclk)) in rs780_set_uvd_clock_after_set_eng_clock()
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| H A D | sumo_dpm.c | 673 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; in sumo_patch_boost_state()
847 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in sumo_set_uvd_clock_before_set_eng_clock()
865 if (new_ps->levels[new_ps->num_levels - 1].sclk < in sumo_set_uvd_clock_after_set_eng_clock()
1190 pi->current_ps = *new_ps; in sumo_update_current_ps()
1201 pi->requested_ps = *new_ps; in sumo_update_requested_ps()
1309 sumo_patch_boost_state(rdev, new_ps); in sumo_dpm_set_power_state()
1318 sumo_program_wl(rdev, new_ps); in sumo_dpm_set_power_state()
1319 sumo_program_bsp(rdev, new_ps); in sumo_dpm_set_power_state()
1320 sumo_program_at(rdev, new_ps); in sumo_dpm_set_power_state()
1321 sumo_force_nbp_state(rdev, new_ps); in sumo_dpm_set_power_state()
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| H A D | rv6xx_dpm.c | 967 struct radeon_ps *new_ps, in rv6xx_enable_static_voltage_control() argument
1047 struct radeon_ps *new_ps) in rv6xx_calculate_stepping_parameters() argument
1200 struct radeon_ps *new_ps, in rv6xx_set_sw_voltage_to_safe() argument
1230 struct radeon_ps *new_ps, in rv6xx_set_safe_backbias() argument
1244 struct radeon_ps *new_ps, in rv6xx_set_safe_pcie_gen2() argument
1306 struct radeon_ps *new_ps, in rv6xx_step_voltage_if_increasing() argument
1433 struct radeon_ps *new_ps) in rv6xx_generate_low_step() argument
1453 struct radeon_ps *new_ps) in rv6xx_generate_stepping_table() argument
1495 struct radeon_ps *new_ps, in rv6xx_enable_dynamic_pcie_gen2() argument
1526 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
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| H A D | trinity_dpm.c | 853 for (i = 0; i < new_ps->num_levels; i++) { in trinity_program_power_levels_0_to_n()
974 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
988 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
1079 pi->current_ps = *new_ps; in trinity_update_current_ps()
1090 pi->requested_ps = *new_ps; in trinity_update_requested_ps()
1200 DpmXNbPsLo(new_ps->DpmXNbPsLo) | in trinity_setup_nbp_sim()
1201 DpmXNbPsHi(new_ps->DpmXNbPsHi)); in trinity_setup_nbp_sim()
1241 struct radeon_ps *new_ps = &requested_ps; in trinity_dpm_pre_set_power_state() local
1243 trinity_update_requested_ps(rdev, new_ps); in trinity_dpm_pre_set_power_state()
1266 trinity_setup_nbp_sim(rdev, new_ps); in trinity_dpm_set_power_state()
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| H A D | kv_dpm.c | 1138 struct kv_ps *new_ps = kv_get_ps(rps); in kv_update_current_ps() local
1142 pi->current_ps = *new_ps; in kv_update_current_ps()
1149 struct kv_ps *new_ps = kv_get_ps(rps); in kv_update_requested_ps() local
1153 pi->requested_ps = *new_ps; in kv_update_requested_ps()
1721 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1728 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1747 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1753 if ((new_ps->levels[0].sclk - in kv_set_valid_clock_range()
1756 new_ps->levels[new_ps->num_levels -1].sclk)) in kv_set_valid_clock_range()
1840 kv_update_requested_ps(rdev, new_ps); in kv_dpm_pre_set_power_state()
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| H A D | btc_dpm.c | 2258 struct rv7xx_ps *new_ps = rv770_get_ps(rps); in btc_update_current_ps() local
2262 eg_pi->current_ps = *new_ps; in btc_update_current_ps()
2269 struct rv7xx_ps *new_ps = rv770_get_ps(rps); in btc_update_requested_ps() local
2273 eg_pi->requested_ps = *new_ps; in btc_update_requested_ps()
2291 struct radeon_ps *new_ps = &requested_ps; in btc_dpm_pre_set_power_state() local
2293 btc_update_requested_ps(rdev, new_ps); in btc_dpm_pre_set_power_state()
2303 struct radeon_ps *new_ps = &eg_pi->requested_rps; in btc_dpm_set_power_state() local
2323 btc_set_at_for_uvd(rdev, new_ps); in btc_dpm_set_power_state()
2325 btc_notify_uvd_to_smc(rdev, new_ps); in btc_dpm_set_power_state()
2326 ret = cypress_upload_sw_state(rdev, new_ps); in btc_dpm_set_power_state()
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| H A D | ni_dpm.c | 3507 struct radeon_ps *new_ps, in ni_set_uvd_clock_before_set_eng_clock() argument
3513 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_before_set_eng_clock()
3514 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_before_set_eng_clock()
3521 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3525 struct radeon_ps *new_ps, in ni_set_uvd_clock_after_set_eng_clock() argument
3531 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_after_set_eng_clock()
3532 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_after_set_eng_clock()
3539 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock()
3567 ni_pi->current_ps = *new_ps; in ni_update_current_ps()
3579 ni_pi->requested_ps = *new_ps; in ni_update_requested_ps()
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| H A D | rv770_dpm.c | 1437 struct radeon_ps *new_ps, in rv770_set_uvd_clock_before_set_eng_clock() argument
1440 struct rv7xx_ps *new_state = rv770_get_ps(new_ps); in rv770_set_uvd_clock_before_set_eng_clock()
1443 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_before_set_eng_clock()
1444 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_before_set_eng_clock()
1450 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1454 struct radeon_ps *new_ps, in rv770_set_uvd_clock_after_set_eng_clock() argument
1457 struct rv7xx_ps *new_state = rv770_get_ps(new_ps); in rv770_set_uvd_clock_after_set_eng_clock()
1460 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_after_set_eng_clock()
1461 (new_ps->dclk == old_ps->dclk)) in rv770_set_uvd_clock_after_set_eng_clock()
1467 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
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| H A D | ni_dpm.h | 242 struct radeon_ps *new_ps,
245 struct radeon_ps *new_ps,
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| H A D | rv770_dpm.h | 273 struct radeon_ps *new_ps,
276 struct radeon_ps *new_ps,
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| H A D | cypress_dpm.c | 1957 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in cypress_dpm_set_power_state() local
1967 cypress_notify_link_speed_change_before_state_change(rdev, new_ps, old_ps); in cypress_dpm_set_power_state()
1969 rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); in cypress_dpm_set_power_state()
1975 ret = cypress_upload_sw_state(rdev, new_ps); in cypress_dpm_set_power_state()
1981 ret = cypress_upload_mc_reg_table(rdev, new_ps); in cypress_dpm_set_power_state()
1988 cypress_program_memory_timing_parameters(rdev, new_ps); in cypress_dpm_set_power_state()
2000 rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); in cypress_dpm_set_power_state()
2003 cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); in cypress_dpm_set_power_state()
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| H A D | si_dpm.c | 6520 struct radeon_ps *new_ps = &requested_ps; in si_dpm_pre_set_power_state() local
6522 ni_update_requested_ps(rdev, new_ps); in si_dpm_pre_set_power_state()
6540 ret = si_populate_smc_tdp_limits(rdev, new_ps); in si_power_control_set_level()
6543 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); in si_power_control_set_level()
6558 struct radeon_ps *new_ps = &eg_pi->requested_rps; in si_dpm_set_power_state() local
6580 ret = si_enable_smc_cac(rdev, new_ps, false); in si_dpm_set_power_state()
6590 ret = si_upload_sw_state(rdev, new_ps); in si_dpm_set_power_state()
6606 ret = si_upload_mc_reg_table(rdev, new_ps); in si_dpm_set_power_state()
6630 si_set_vce_clock(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6638 ret = si_enable_smc_cac(rdev, new_ps, true); in si_dpm_set_power_state()
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| H A D | ci_dpm.c | 5140 struct ci_ps *new_ps = ci_get_ps(rps); in ci_update_current_ps() local
5144 pi->current_ps = *new_ps; in ci_update_current_ps()
5151 struct ci_ps *new_ps = ci_get_ps(rps); in ci_update_requested_ps() local
5155 pi->requested_ps = *new_ps; in ci_update_requested_ps()
5163 struct radeon_ps *new_ps = &requested_ps; in ci_dpm_pre_set_power_state() local
5165 ci_update_requested_ps(rdev, new_ps); in ci_dpm_pre_set_power_state()
5175 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_post_set_power_state() local
5177 ci_update_current_ps(rdev, new_ps); in ci_dpm_post_set_power_state()
5383 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_set_power_state() local
5387 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps); in ci_dpm_set_power_state()
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| /dragonfly/sys/dev/drm/amd/powerplay/hwmgr/ |
| H A D | pp_psm.c | 235 struct pp_power_state *new_ps) in power_state_management() argument
241 if (new_ps != NULL) in power_state_management()
242 requested = new_ps; in power_state_management()
260 struct pp_power_state *new_ps) in psm_adjust_power_state_dynamic() argument
271 power_state_management(hwmgr, new_ps); in psm_adjust_power_state_dynamic()
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| H A D | pp_psm.h | 38 struct pp_power_state *new_ps);
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | si_dpm.c | 3152 ni_pi->current_ps = *new_ps; in ni_update_current_ps()
3165 ni_pi->requested_ps = *new_ps; in ni_update_requested_ps()
3171 struct amdgpu_ps *new_ps, in ni_set_uvd_clock_before_set_eng_clock() argument
3177 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_before_set_eng_clock()
3178 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_before_set_eng_clock()
3185 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3189 struct amdgpu_ps *new_ps, in ni_set_uvd_clock_after_set_eng_clock() argument
3195 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_after_set_eng_clock()
3196 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_after_set_eng_clock()
3203 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock()
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