| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | amdgpu_irq.c | 133 if (!src || !src->funcs->set || !src->num_types) in amdgpu_irq_disable_all()
136 for (k = 0; k < src->num_types; ++k) { in amdgpu_irq_disable_all()
345 if (source->num_types && !source->enabled_types) { in amdgpu_irq_add_id()
348 types = kcalloc(source->num_types, sizeof(atomic_t), in amdgpu_irq_add_id()
464 for (k = 0; k < src->num_types; k++) in amdgpu_irq_gpu_reset_resume_helper()
488 if (type >= src->num_types) in amdgpu_irq_get()
518 if (type >= src->num_types) in amdgpu_irq_put()
549 if (type >= src->num_types) in amdgpu_irq_enabled()
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| H A D | mxgpu_ai.c | 324 adev->virt.ack_irq.num_types = 1; in xgpu_ai_mailbox_set_irq_funcs()
326 adev->virt.rcv_irq.num_types = 1; in xgpu_ai_mailbox_set_irq_funcs()
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| H A D | amdgpu_irq.h | 42 unsigned num_types; member
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| H A D | mxgpu_vi.c | 572 adev->virt.ack_irq.num_types = 1; in xgpu_vi_mailbox_set_irq_funcs()
574 adev->virt.rcv_irq.num_types = 1; in xgpu_vi_mailbox_set_irq_funcs()
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| H A D | uvd_v6_0.c | 420 adev->uvd.inst->irq.num_types = 1; in uvd_v6_0_sw_init()
1638 adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1; in uvd_v6_0_set_irq_funcs()
1640 adev->uvd.inst->irq.num_types = 1; in uvd_v6_0_set_irq_funcs()
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| H A D | dce_virtual.c | 765 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VBLANK6 + 1; in dce_virtual_set_irq_funcs()
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| H A D | uvd_v5_0.c | 891 adev->uvd.inst->irq.num_types = 1; in uvd_v5_0_set_irq_funcs()
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| H A D | dce_v10_0.c | 3583 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; in dce_v10_0_set_irq_funcs()
3585 adev->crtc_irq.num_types = 0; in dce_v10_0_set_irq_funcs()
3588 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; in dce_v10_0_set_irq_funcs()
3591 adev->hpd_irq.num_types = adev->mode_info.num_hpd; in dce_v10_0_set_irq_funcs()
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| H A D | dce_v11_0.c | 3715 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; in dce_v11_0_set_irq_funcs()
3717 adev->crtc_irq.num_types = 0; in dce_v11_0_set_irq_funcs()
3720 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; in dce_v11_0_set_irq_funcs()
3723 adev->hpd_irq.num_types = adev->mode_info.num_hpd; in dce_v11_0_set_irq_funcs()
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| H A D | gmc_v9_0.c | 290 adev->gmc.vm_fault.num_types = 1; in gmc_v9_0_set_irq_funcs()
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| H A D | vce_v3_0.c | 969 adev->vce.irq.num_types = 1; in vce_v3_0_set_irq_funcs()
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| H A D | vce_v4_0.c | 1113 adev->vce.irq.num_types = 1; in vce_v4_0_set_irq_funcs()
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| H A D | sdma_v2_4.c | 1233 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; in sdma_v2_4_set_irq_funcs()
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| H A D | gfx_v8_0.c | 7308 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v8_0_set_irq_funcs()
7311 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7314 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7317 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; in gfx_v8_0_set_irq_funcs()
7320 adev->gfx.cp_ecc_error_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
7323 adev->gfx.sq_irq.num_types = 1; in gfx_v8_0_set_irq_funcs()
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| H A D | gmc_v7_0.c | 1401 adev->gmc.vm_fault.num_types = 1; in gmc_v7_0_set_irq_funcs()
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| H A D | gfx_v9_0.c | 4772 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v9_0_set_irq_funcs()
4775 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v9_0_set_irq_funcs()
4778 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v9_0_set_irq_funcs()
4781 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; in gfx_v9_0_set_irq_funcs()
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| H A D | gmc_v8_0.c | 1768 adev->gmc.vm_fault.num_types = 1; in gmc_v8_0_set_irq_funcs()
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| H A D | sdma_v3_0.c | 1673 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; in sdma_v3_0_set_irq_funcs()
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| /dragonfly/sys/dev/drm/amd/include/ |
| H A D | cgs_linux.h | 70 unsigned num_types,
110 #define cgs_add_irq_source(dev,src_id,num_types,set,handler,private_data) \ argument
111 CGS_OS_CALL(add_irq_source,dev,src_id,num_types,set,handler, \
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| /dragonfly/contrib/wpa_supplicant/src/eap_peer/ |
| H A D | eap_tls_common.h | 136 size_t *num_types);
137 int eap_peer_tls_phase2_nak(struct eap_method_type *types, size_t num_types,
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| H A D | eap_tls_common.c | 1095 size_t *num_types) in eap_peer_select_phase2_methods() argument
1164 *num_types = num_methods; in eap_peer_select_phase2_methods()
1178 int eap_peer_tls_phase2_nak(struct eap_method_type *types, size_t num_types, in eap_peer_tls_phase2_nak() argument
1187 (u8 *) types, num_types * sizeof(struct eap_method_type)); in eap_peer_tls_phase2_nak()
1188 *resp = eap_msg_alloc(EAP_VENDOR_IETF, EAP_TYPE_NAK, num_types, in eap_peer_tls_phase2_nak()
1193 for (i = 0; i < num_types; i++) { in eap_peer_tls_phase2_nak()
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| /dragonfly/sys/dev/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_irq.c | 615 adev->crtc_irq.num_types = adev->mode_info.num_crtc; in amdgpu_dm_set_irq_funcs()
618 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; in amdgpu_dm_set_irq_funcs()
621 adev->hpd_irq.num_types = adev->mode_info.num_hpd; in amdgpu_dm_set_irq_funcs()
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| /dragonfly/contrib/gdb-7/gdb/ |
| H A D | eval.c | 657 make_params (int num_types, struct type **param_types) in make_params() argument
665 if (num_types > 0) in make_params()
667 if (param_types[num_types - 1] == NULL) in make_params()
669 --num_types; in make_params()
672 else if (TYPE_CODE (check_typedef (param_types[num_types - 1])) in make_params()
675 --num_types; in make_params()
677 gdb_assert (num_types == 0); in make_params()
682 TYPE_NFIELDS (type) = num_types; in make_params()
684 TYPE_ZALLOC (type, sizeof (struct field) * num_types); in make_params()
686 while (num_types-- > 0) in make_params()
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| H A D | std-operator.def | 69 TYPE_INSTANCE num_types type0 ... typeN num_types TYPE_INSTANCE. */
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| /dragonfly/sys/dev/drm/i915/gvt/ |
| H A D | gvt.h | 274 unsigned int num_types; member
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