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Searched refs:out_reg (Results 1 – 19 of 19) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Diceland_smumgr.c2378 *out_reg = mmMC_SEQ_RAS_TIMING_LP; in iceland_check_s0_mc_reg_index()
2382 *out_reg = mmMC_SEQ_DLL_STBY_LP; in iceland_check_s0_mc_reg_index()
2386 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP; in iceland_check_s0_mc_reg_index()
2390 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP; in iceland_check_s0_mc_reg_index()
2394 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP; in iceland_check_s0_mc_reg_index()
2398 *out_reg = mmMC_SEQ_CAS_TIMING_LP; in iceland_check_s0_mc_reg_index()
2418 *out_reg = mmMC_SEQ_RD_CTL_D0_LP; in iceland_check_s0_mc_reg_index()
2422 *out_reg = mmMC_SEQ_RD_CTL_D1_LP; in iceland_check_s0_mc_reg_index()
2426 *out_reg = mmMC_SEQ_WR_CTL_D0_LP; in iceland_check_s0_mc_reg_index()
2430 *out_reg = mmMC_SEQ_WR_CTL_D1_LP; in iceland_check_s0_mc_reg_index()
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H A Dci_smumgr.c2448 *out_reg = mmMC_SEQ_RAS_TIMING_LP; in ci_check_s0_mc_reg_index()
2452 *out_reg = mmMC_SEQ_DLL_STBY_LP; in ci_check_s0_mc_reg_index()
2456 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP; in ci_check_s0_mc_reg_index()
2460 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP; in ci_check_s0_mc_reg_index()
2464 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP; in ci_check_s0_mc_reg_index()
2468 *out_reg = mmMC_SEQ_CAS_TIMING_LP; in ci_check_s0_mc_reg_index()
2488 *out_reg = mmMC_SEQ_RD_CTL_D0_LP; in ci_check_s0_mc_reg_index()
2492 *out_reg = mmMC_SEQ_RD_CTL_D1_LP; in ci_check_s0_mc_reg_index()
2496 *out_reg = mmMC_SEQ_WR_CTL_D0_LP; in ci_check_s0_mc_reg_index()
2500 *out_reg = mmMC_SEQ_WR_CTL_D1_LP; in ci_check_s0_mc_reg_index()
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H A Dtonga_smumgr.c2829 *out_reg = mmMC_SEQ_RAS_TIMING_LP; in tonga_check_s0_mc_reg_index()
2833 *out_reg = mmMC_SEQ_DLL_STBY_LP; in tonga_check_s0_mc_reg_index()
2837 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP; in tonga_check_s0_mc_reg_index()
2841 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP; in tonga_check_s0_mc_reg_index()
2845 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP; in tonga_check_s0_mc_reg_index()
2849 *out_reg = mmMC_SEQ_CAS_TIMING_LP; in tonga_check_s0_mc_reg_index()
2869 *out_reg = mmMC_SEQ_RD_CTL_D0_LP; in tonga_check_s0_mc_reg_index()
2873 *out_reg = mmMC_SEQ_RD_CTL_D1_LP; in tonga_check_s0_mc_reg_index()
2877 *out_reg = mmMC_SEQ_WR_CTL_D0_LP; in tonga_check_s0_mc_reg_index()
2881 *out_reg = mmMC_SEQ_WR_CTL_D1_LP; in tonga_check_s0_mc_reg_index()
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/dragonfly/sys/dev/drm/radeon/
H A Dbtc_dpm.c1858 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; in btc_check_s0_mc_reg_index()
1861 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; in btc_check_s0_mc_reg_index()
1864 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in btc_check_s0_mc_reg_index()
1867 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; in btc_check_s0_mc_reg_index()
1870 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; in btc_check_s0_mc_reg_index()
1873 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; in btc_check_s0_mc_reg_index()
1876 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; in btc_check_s0_mc_reg_index()
1879 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; in btc_check_s0_mc_reg_index()
1882 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in btc_check_s0_mc_reg_index()
1885 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; in btc_check_s0_mc_reg_index()
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H A Dci_dpm.c4444 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; in ci_check_s0_mc_reg_index()
4447 *out_reg = MC_SEQ_DLL_STBY_LP >> 2; in ci_check_s0_mc_reg_index()
4450 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2; in ci_check_s0_mc_reg_index()
4453 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2; in ci_check_s0_mc_reg_index()
4456 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2; in ci_check_s0_mc_reg_index()
4459 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; in ci_check_s0_mc_reg_index()
4474 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; in ci_check_s0_mc_reg_index()
4477 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; in ci_check_s0_mc_reg_index()
4480 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; in ci_check_s0_mc_reg_index()
4483 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; in ci_check_s0_mc_reg_index()
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H A Dni_dpm.c2772 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; in ni_check_s0_mc_reg_index()
2775 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; in ni_check_s0_mc_reg_index()
2778 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in ni_check_s0_mc_reg_index()
2781 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; in ni_check_s0_mc_reg_index()
2784 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; in ni_check_s0_mc_reg_index()
2787 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; in ni_check_s0_mc_reg_index()
2790 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; in ni_check_s0_mc_reg_index()
2793 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; in ni_check_s0_mc_reg_index()
2796 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in ni_check_s0_mc_reg_index()
2799 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; in ni_check_s0_mc_reg_index()
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H A Dsi_dpm.c5430 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; in si_check_s0_mc_reg_index()
5433 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; in si_check_s0_mc_reg_index()
5436 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in si_check_s0_mc_reg_index()
5439 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; in si_check_s0_mc_reg_index()
5442 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; in si_check_s0_mc_reg_index()
5445 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; in si_check_s0_mc_reg_index()
5448 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; in si_check_s0_mc_reg_index()
5451 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; in si_check_s0_mc_reg_index()
5457 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; in si_check_s0_mc_reg_index()
5463 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; in si_check_s0_mc_reg_index()
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/dragonfly/contrib/gcc-8.0/gcc/
H A Dreload1.c7080 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg) in choose_reload_regs()
7236 rl->out_reg))) in emit_input_reload_insns()
7285 if (rl->out && ! rl->out_reg) in emit_input_reload_insns()
7825 rld[s].out_reg = rl->out_reg; in emit_output_reload_insns()
7966 rtx pseudo = rl->out_reg; in do_output_reload()
8012 old = rl->out_reg; in do_output_reload()
8214 || (rld[r].out_reg in emit_reload_insns()
8215 ? REG_P (rld[r].out_reg) in emit_reload_insns()
8241 : rld[r].out_reg in emit_reload_insns()
8242 ? rld[r].out_reg in emit_reload_insns()
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H A Dreload.h106 rtx out_reg; member
H A Dreload.c483 rld[s_reload].out_reg = 0; in push_secondary_reload()
1373 rld[i].out_reg = outloc ? *outloc : 0; in push_reload()
1463 && (!rld[i].out_reg in push_reload()
1464 || partial_subreg_p (GET_MODE (rld[i].out_reg), in push_reload()
1466 rld[i].out_reg = *outloc; in push_reload()
1830 rld[i].out_reg = rld[output_reload].out_reg; in combine_reloads()
7310 if (rld[r].out_reg != 0) in debug_reload_to_stream()
7313 print_inline_rtx (f, rld[r].out_reg, 24); in debug_reload_to_stream()
/dragonfly/contrib/gcc-4.7/gcc/
H A Dreload1.c7021 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg) in choose_reload_regs()
7175 rl->out_reg))) in emit_input_reload_insns()
7224 if (rl->out && ! rl->out_reg) in emit_input_reload_insns()
7756 rld[s].out_reg = rl->out_reg; in emit_output_reload_insns()
7897 rtx pseudo = rl->out_reg; in do_output_reload()
7943 old = rl->out_reg; in do_output_reload()
8149 || (rld[r].out_reg in emit_reload_insns()
8150 ? REG_P (rld[r].out_reg) in emit_reload_insns()
8176 : rld[r].out_reg in emit_reload_insns()
8177 ? rld[r].out_reg in emit_reload_insns()
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H A Dreload.h106 rtx out_reg; member
H A Dreload.c496 rld[s_reload].out_reg = 0; in push_secondary_reload()
1352 rld[i].out_reg = outloc ? *outloc : 0; in push_reload()
1446 && (!rld[i].out_reg in push_reload()
1448 > GET_MODE_SIZE (GET_MODE (rld[i].out_reg)))) in push_reload()
1449 rld[i].out_reg = *outloc; in push_reload()
1814 rld[i].out_reg = rld[output_reload].out_reg; in combine_reloads()
7349 if (rld[r].out_reg != 0) in debug_reload_to_stream()
7352 print_inline_rtx (f, rld[r].out_reg, 24); in debug_reload_to_stream()
/dragonfly/sys/dev/netif/ix/
H A Dixgbe_common.h172 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg);
H A Dixgbe_api.c1377 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg)
1380 (in_reg, out_reg), IXGBE_NOT_IMPLEMENTED);
H A Dixgbe_api.h203 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg);
H A Dixgbe_common.c4969 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg) in ixgbe_bypass_valid_rd_generic() argument
4974 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M)) in ixgbe_bypass_valid_rd_generic()
4987 if ((out_reg & mask) != (in_reg & mask)) in ixgbe_bypass_valid_rd_generic()
4991 if (!(out_reg & BYPASS_STATUS_OFF_M)) in ixgbe_bypass_valid_rd_generic()
5000 if ((out_reg & mask) != (in_reg & mask)) in ixgbe_bypass_valid_rd_generic()
H A Dixgbe_type.h3979 bool (*bypass_valid_rd) (u32 in_reg, u32 out_reg);
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsi_dpm.c5885 *out_reg = MC_SEQ_RAS_TIMING_LP; in si_check_s0_mc_reg_index()
5888 *out_reg = MC_SEQ_CAS_TIMING_LP; in si_check_s0_mc_reg_index()
5891 *out_reg = MC_SEQ_MISC_TIMING_LP; in si_check_s0_mc_reg_index()
5894 *out_reg = MC_SEQ_MISC_TIMING2_LP; in si_check_s0_mc_reg_index()
5897 *out_reg = MC_SEQ_RD_CTL_D0_LP; in si_check_s0_mc_reg_index()
5900 *out_reg = MC_SEQ_RD_CTL_D1_LP; in si_check_s0_mc_reg_index()
5903 *out_reg = MC_SEQ_WR_CTL_D0_LP; in si_check_s0_mc_reg_index()
5906 *out_reg = MC_SEQ_WR_CTL_D1_LP; in si_check_s0_mc_reg_index()
5912 *out_reg = MC_SEQ_PMG_CMD_MRS_LP; in si_check_s0_mc_reg_index()
5918 *out_reg = MC_SEQ_PMG_TIMING_LP; in si_check_s0_mc_reg_index()
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