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Searched refs:p2pll_div_0 (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dradeon_legacy_tv.c906 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl) in radeon_legacy_tv_adjust_pll2() argument
919 *p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); in radeon_legacy_tv_adjust_pll2()
H A Dradeon_mode.h971 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);