| /dragonfly/sys/dev/drm/amd/display/dc/core/ |
| H A D | dc.c | 649 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
689 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
735 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
738 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
760 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
763 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
770 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
783 for (j = i + 1; j < pipe_count; j++) { in program_timing_sync()
908 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_commit_state_no_check()
1029 for (i = 0; i < dc->res_pool->pipe_count; i++) in dc_post_update_surfaces_to_stream()
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| H A D | dc_debug.c | 320 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in context_timing_trace()
333 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in context_timing_trace()
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| H A D | dc_surface.c | 118 for (i = 0; i < core_dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
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| H A D | dc_resource.c | 1159 for (i = pool->pipe_count - 1; i >= 0; i--) { in find_idle_secondary_pipe()
1233 for (i = pool->pipe_count - 1; i >= 0; i--) { in acquire_free_pipe_for_stream()
1260 for (i = 0; i < pool->pipe_count; i++) { in acquire_first_split_pipe()
1382 for (i = pool->pipe_count - 1; i >= 0; i--) { in dc_remove_plane_from_context()
1636 for (i = 0; i < pool->pipe_count; i++) { in acquire_first_free_pipe()
2019 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dc_validate_global_state()
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| /dragonfly/sys/dev/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hw_sequencer.c | 127 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
159 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
184 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
216 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
249 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
288 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
565 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
745 for (i = 0; i < dc->res_pool->pipe_count; i++) in reset_back_end_for_pipe()
749 if (i == dc->res_pool->pipe_count) in reset_back_end_for_pipe()
2365 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn10_apply_ctx_for_surface()
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| H A D | dcn10_resource.c | 843 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
1126 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in construct()
1254 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
1314 pool->base.pipe_count = j; in construct()
1320 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in construct()
1321 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in construct()
1343 dc->caps.max_planes = pool->base.pipe_count; in construct()
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| /dragonfly/sys/dev/drm/amd/display/dc/dce110/ |
| H A D | dce110_resource.c | 671 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
824 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1074 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1075 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1076 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1077 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1078 pool->pipe_count++; in underlay_create()
1174 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in construct()
1175 pool->base.underlay_pipe_index = pool->base.pipe_count; in construct()
1264 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
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| H A D | dce110_hw_sequencer.c | 1546 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vga_and_power_gate_all_controllers()
1836 for (i = 0; i < dc->res_pool->pipe_count; i++) { in should_enable_fbc()
1971 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_setup_audio_dto()
1998 if (i == dc->res_pool->pipe_count) { in dce110_setup_audio_dto()
2047 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_to_hw()
2072 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_to_hw()
2365 for (i = 0; i < dc->res_pool->pipe_count; i++) { in init_hw()
2396 for (i = 0; i < dc->res_pool->pipe_count; i++) { in init_hw()
2738 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_for_surface()
2749 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce110_apply_ctx_for_surface()
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| /dragonfly/sys/dev/drm/amd/display/dc/dce80/ |
| H A D | dce80_resource.c | 678 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
818 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
910 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
956 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1011 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1104 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1142 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1197 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1286 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
1324 dc->caps.max_planes = pool->base.pipe_count; in dce83_construct()
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| /dragonfly/sys/dev/drm/amd/display/dc/dce100/ |
| H A D | dce100_resource.c | 646 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
727 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce100_validate_bandwidth()
925 pool->base.pipe_count = res_cap.num_timing_generator; in construct()
932 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
984 dc->caps.max_planes = pool->base.pipe_count; in construct()
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| /dragonfly/sys/dev/drm/amd/display/dc/dce120/ |
| H A D | dce120_resource.c | 483 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
883 pool->base.pipe_count = res_cap.num_timing_generator; in construct()
976 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
1041 pool->base.pipe_count = j; in construct()
1052 dc->caps.max_planes = pool->base.pipe_count; in construct()
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| /dragonfly/sys/dev/drm/amd/display/dc/dce112/ |
| H A D | dce112_resource.c | 665 for (i = 0; i < pool->base.pipe_count; i++) { in destruct()
781 dc->res_pool->pipe_count, in dce112_validate_bandwidth()
1111 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in construct()
1213 for (i = 0; i < pool->base.pipe_count; i++) { in construct()
1271 dc->caps.max_planes = pool->base.pipe_count; in construct()
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| /dragonfly/sys/dev/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 148 unsigned int pipe_count; member
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| H A D | dce_calcs.h | 485 int pipe_count,
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| /dragonfly/sys/dev/drm/amd/display/dc/dce/ |
| H A D | dce_clocks.c | 548 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn1_ramp_up_dispclk_with_dpp()
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| /dragonfly/sys/dev/drm/amd/display/dc/calcs/ |
| H A D | dcn_calcs.c | 830 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) { in dcn_validate_bandwidth()
1082 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) { in dcn_validate_bandwidth()
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| H A D | dce_calcs.c | 2757 const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data) in populate_initial_data() argument
2773 for (i = 0; i < pipe_count; i++) { in populate_initial_data()
2883 for (i = 0; i < pipe_count; i++) { in populate_initial_data()
2985 int pipe_count, in bw_calcs() argument
2993 populate_initial_data(pipe, pipe_count, data); in bw_calcs()
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