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Searched refs:pipe_offset (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/irq/dce110/
H A Dirq_service_dce110.c205 uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; in dce110_vblank_set() local
208 core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; in dce110_vblank_set()
/dragonfly/sys/dev/drm/radeon/
H A Devergreen.c1811 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in evergreen_line_buffer_adjust() local
1852 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in evergreen_line_buffer_adjust()
1855 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in evergreen_line_buffer_adjust()
2147 u32 pipe_offset = radeon_crtc->crtc_id * 16; in evergreen_program_watermarks() local
2266 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2270 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2271 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
2275 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2278 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2279 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
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H A Dsi.c1963 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce6_line_buffer_adjust() local
1993 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce6_line_buffer_adjust()
1996 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce6_line_buffer_adjust()
H A Dcik.c8791 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce8_line_buffer_adjust() local
8823 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce8_line_buffer_adjust()
8826 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce8_line_buffer_adjust()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c585 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v10_0_line_buffer_adjust() local
618 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v10_0_line_buffer_adjust()
620 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); in dce_v10_0_line_buffer_adjust()
623 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v10_0_line_buffer_adjust()
H A Ddce_v11_0.c611 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v11_0_line_buffer_adjust() local
644 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v11_0_line_buffer_adjust()
646 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); in dce_v11_0_line_buffer_adjust()
649 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v11_0_line_buffer_adjust()