| /dragonfly/usr.sbin/kbdcontrol/ |
| H A D | kbdcontrol.c | 864 int bell, duration = 0, pitch = 0; in set_bell_values() local
874 duration = 5, pitch = 800; in set_bell_values()
876 duration = 0, pitch = 0; in set_bell_values()
885 pitch = strtol(opt, &v1, 0); in set_bell_values()
886 if ((pitch < 0) || (*opt == '\0') || (*v1 != '\0')) { in set_bell_values()
891 if (pitch != 0) in set_bell_values()
892 pitch = 1193182 / pitch; /* in Hz */ in set_bell_values()
898 fprintf(stderr, "[=%d;%dB", pitch, duration); in set_bell_values()
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| /dragonfly/sys/dev/drm/radeon/ |
| H A D | r100_track.h | 14 unsigned pitch; member
38 unsigned pitch; member
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| H A D | r600_cs.c | 375 height = slice_tile_max / pitch; in r600_cs_track_validate_cb()
413 if (!IS_ALIGNED(pitch, pitch_align)) { in r600_cs_track_validate_cb()
456 pitch, height, r600_fmt_get_nblocksx(format, pitch), in r600_cs_track_validate_cb()
463 tmp = (height * pitch) >> 6; in r600_cs_track_validate_cb()
466 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) | in r600_cs_track_validate_cb()
522 u32 pitch = 8192; in r600_cs_track_validate_db() local
572 height = slice_tile_max / pitch; in r600_cs_track_validate_db()
604 if (!IS_ALIGNED(pitch, pitch_align)) { in r600_cs_track_validate_db()
648 nbx = pitch; in r600_cs_track_validate_db()
1508 pitch = (G_038000_PITCH(word0) + 1) * 8; in r600_check_texture_resource()
[all …]
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| H A D | radeon_object.c | 652 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg()
674 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument
728 bo->pitch = pitch; in radeon_bo_set_tiling_flags()
735 uint32_t *pitch) in radeon_bo_get_tiling_flags() argument
741 if (pitch) in radeon_bo_get_tiling_flags()
742 *pitch = bo->pitch; in radeon_bo_get_tiling_flags()
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| H A D | radeon_object.h | 147 u32 tiling_flags, u32 pitch);
149 u32 *tiling_flags, u32 *pitch);
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| H A D | r100.c | 894 uint32_t pitch; in r100_copy_blit() local
903 pitch = stride_bytes / 64; in r100_copy_blit()
2290 track->zb.pitch, track->zb.cpp, in r100_cs_track_check()
2310 i, track->aa.pitch, track->cb[0].cpp, in r100_cs_track_check()
2412 track->cb[i].pitch = 8192; in r100_cs_track_clear()
2418 track->zb.pitch = 8192; in r100_cs_track_clear()
2431 track->textures[i].pitch = 16536; in r100_cs_track_clear()
3104 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument
3119 pitch = 0; in r100_set_surface_reg()
3139 flags |= pitch / 16; in r100_set_surface_reg()
[all …]
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| H A D | r200.c | 304 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; in r200_packet0_check()
308 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; in r200_packet0_check()
409 track->textures[i].pitch = idx_value + 32; in r200_packet0_check()
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| H A D | radeon_gem.c | 517 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl()
538 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
765 args->pitch = radeon_align_pitch(rdev, args->width, in radeon_mode_dumb_create()
767 args->size = args->pitch * args->height; in radeon_mode_dumb_create()
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| H A D | r300.c | 794 track->cb[i].pitch = idx_value & 0x3FFE; in r300_packet0_check()
878 track->zb.pitch = idx_value & 0x3FFC; in r300_packet0_check()
1024 track->textures[i].pitch = tmp + 1; in r300_packet0_check()
1129 track->aa.pitch = idx_value & 0x3FFE; in r300_packet0_check()
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| H A D | evergreen_cs.c | 396 unsigned pitch, slice, mslice; in evergreen_cs_track_validate_cb() local
401 pitch = track->cb_color_pitch[id]; in evergreen_cs_track_validate_cb()
403 surf.nbx = (pitch + 1) * 8; in evergreen_cs_track_validate_cb()
563 unsigned pitch, slice, mslice; in evergreen_cs_track_validate_stencil() local
568 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); in evergreen_cs_track_validate_stencil()
570 surf.nbx = (pitch + 1) * 8; in evergreen_cs_track_validate_stencil()
660 unsigned pitch, slice, mslice; in evergreen_cs_track_validate_depth() local
665 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); in evergreen_cs_track_validate_depth()
667 surf.nbx = (pitch + 1) * 8; in evergreen_cs_track_validate_depth()
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| H A D | radeon_uvd.c | 360 unsigned pitch = msg[28]; in radeon_uvd_cs_msg_decode() local
426 if (width > pitch) { in radeon_uvd_cs_msg_decode()
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| /dragonfly/sys/dev/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hubp.c | 162 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c; in hubp1_program_size() local
171 pitch = plane_size->video.luma_pitch - 1; in hubp1_program_size()
176 pitch = plane_size->grph.surface_pitch - 1; in hubp1_program_size()
188 PITCH, pitch, META_PITCH, meta_pitch); in hubp1_program_size()
989 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch) in hubp1_get_cursor_pitch() argument
993 switch (pitch) { in hubp1_get_cursor_pitch()
1005 "Only 64/128/256 is supported on DCN.\n", pitch); in hubp1_get_cursor_pitch()
1038 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch); in hubp1_cursor_set_attributes()
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| /dragonfly/sys/platform/pc64/include/ |
| H A D | clock.h | 57 int sysbeep (int pitch, int period);
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| /dragonfly/sys/dev/drm/include/drm/ |
| H A D | drm_fb_helper.h | 263 void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch,
376 static inline void drm_fb_helper_fill_fix(struct fb_info *info, uint32_t pitch, in drm_fb_helper_fill_fix() argument
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| /dragonfly/sys/dev/drm/ |
| H A D | drm_dumb_buffers.c | 88 args->pitch = 0; in drm_mode_create_dumb_ioctl()
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| H A D | drm_framebuffer.c | 117 r.pitches[0] = or->pitch; in drm_mode_addfb()
471 r->pitch = fb->pitches[0]; in drm_mode_getfb()
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| /dragonfly/sys/dev/drm/include/uapi/drm/ |
| H A D | radeon_drm.h | 678 int pitch; member
859 __u32 pitch; member
865 __u32 pitch; member
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| H A D | drm_mode.h | 485 __u32 pitch; member
723 __u32 pitch; member
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| H A D | i915_drm.h | 111 unsigned int pitch; member
148 int pitch; member
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| /dragonfly/sys/dev/video/bktr/ |
| H A D | bktr_core.c | 2627 volatile uint32_t pitch; in rgb_vbi_prog() local
2672 pitch = bktr->video.width; in rgb_vbi_prog()
2676 pitch = cols*Bpp; in rgb_vbi_prog()
2728 target_buffer += interlace * pitch; in rgb_vbi_prog()
2753 target_buffer = buffer+pitch; in rgb_vbi_prog()
2784 target_buffer += interlace * pitch; in rgb_vbi_prog()
2807 volatile uint32_t pitch; in rgb_prog() local
2842 pitch = bktr->video.width; in rgb_prog()
2846 pitch = cols*Bpp; in rgb_prog()
2881 target_buffer += interlace * pitch; in rgb_prog()
[all …]
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| /dragonfly/sys/dev/netif/mn/ |
| H A D | if_mn.c | 580 int chan, pitch, len; in ngmn_rcvdata() local
595 pitch = 0; in ngmn_rcvdata()
602 pitch++; in ngmn_rcvdata()
632 if (pitch) in ngmn_rcvdata()
634 sc->name, chan, pitch); in ngmn_rcvdata()
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| /dragonfly/sys/platform/pc64/isa/ |
| H A D | clock.c | 505 sysbeep(int pitch, int period) in sysbeep() argument
514 outb(TIMER_CNTR2, pitch); in sysbeep()
515 outb(TIMER_CNTR2, (pitch>>8)); in sysbeep()
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| /dragonfly/sys/dev/drm/amd/display/dc/ |
| H A D | dc_hw_types.h | 490 uint32_t pitch; member
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | amdgpu_gem.c | 775 args->pitch = amdgpu_align_pitch(adev, args->width, in amdgpu_mode_dumb_create()
777 args->size = (u64)args->pitch * args->height; in amdgpu_mode_dumb_create()
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| H A D | amdgpu_uvd.c | 521 unsigned pitch = msg[28]; in amdgpu_uvd_cs_msg_decode() local
681 if (width > pitch) { in amdgpu_uvd_cs_msg_decode()
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