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Searched refs:pixclks_cntl (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dradeon_legacy_crtc.c857 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) & in radeon_set_pll() local
864 &pixclks_cntl); in radeon_set_pll()
919 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); in radeon_set_pll()
921 uint32_t pixclks_cntl; in radeon_set_pll() local
925 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_set_pll()
927 &pll_fb_post_div, &pixclks_cntl); in radeon_set_pll()
1025 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); in radeon_set_pll()
H A Dradeon_legacy_tv.c886 uint32_t *ppll_div_3, uint32_t *pixclks_cntl) in radeon_legacy_tv_adjust_pll1() argument
900 *pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL); in radeon_legacy_tv_adjust_pll1()
901 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK; in radeon_legacy_tv_adjust_pll1()
906 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl) in radeon_legacy_tv_adjust_pll2() argument
920 *pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK; in radeon_legacy_tv_adjust_pll2()
921 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL; in radeon_legacy_tv_adjust_pll2()
H A Dradeon_legacy_encoders.c49 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; in radeon_legacy_lvds_update() local
108 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_lvds_update()
121 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); in radeon_legacy_lvds_update()
1537 uint32_t gpiopad_a = 0, pixclks_cntl, tmp; in radeon_legacy_tv_dac_detect() local
1583 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); in radeon_legacy_tv_dac_detect()
1600 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb in radeon_legacy_tv_dac_detect()
1676 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); in radeon_legacy_tv_dac_detect()
H A Dradeon_mode.h968 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
971 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);