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Searched refs:pll_dw0 (Results 1 – 1 of 1) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_display.c7461 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; in chv_crtc_clock_get() local
7470 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); in chv_crtc_clock_get()
7477 clock.m2 = (pll_dw0 & 0xff) << 22; in chv_crtc_clock_get()