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Searched refs:rb_bufsz (Results 1 – 23 of 23) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Duvd_v1_0.c266 uint32_t rb_bufsz; in uvd_v1_0_start() local
377 rb_bufsz = order_base_2(ring->ring_size); in uvd_v1_0_start()
378 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v1_0_start()
379 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v1_0_start()
H A Dr600_dma.c122 u32 rb_bufsz; in r600_dma_resume() local
129 rb_bufsz = order_base_2(ring->ring_size / 4); in r600_dma_resume()
130 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
H A Dni_dma.c189 u32 rb_bufsz; in cayman_dma_resume() local
208 rb_bufsz = order_base_2(ring->ring_size / 4); in cayman_dma_resume()
209 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
H A Dcik_sdma.c367 u32 rb_bufsz; in cik_sdma_gfx_resume() local
386 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
387 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
H A Dr600.c2729 u32 rb_bufsz; in r600_cp_resume() local
2739 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()
2791 u32 rb_bufsz; in r600_ring_init() local
2795 rb_bufsz = order_base_2(ring_size / 8); in r600_ring_init()
2796 ring_size = (1 << (rb_bufsz + 1)) * 4; in r600_ring_init()
3482 u32 rb_bufsz; in r600_ih_ring_init() local
3485 rb_bufsz = order_base_2(ring_size / 4); in r600_ih_ring_init()
3486 ring_size = (1 << rb_bufsz) * 4; in r600_ih_ring_init()
3688 int rb_bufsz; in r600_irq_init() local
3722 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in r600_irq_init()
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H A Dsi.c3638 u32 rb_bufsz; in si_cp_resume() local
3655 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3656 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
3686 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3687 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
3710 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3711 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in si_cp_resume()
5967 int rb_bufsz; in si_irq_init() local
5998 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in si_irq_init()
6002 (rb_bufsz << 1)); in si_irq_init()
H A Dr100.c1123 unsigned rb_bufsz; in r100_cp_init() local
1145 rb_bufsz = order_base_2(ring_size / 8); in r100_cp_init()
1146 ring_size = (1 << (rb_bufsz + 1)) * 4; in r100_cp_init()
1179 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | in r100_cp_init()
H A Dcik.c4090 u32 rb_bufsz; in cik_cp_gfx_resume() local
4109 rb_bufsz = order_base_2(ring->ring_size / 8); in cik_cp_gfx_resume()
4110 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in cik_cp_gfx_resume()
6986 int rb_bufsz; in cik_irq_init() local
7017 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in cik_irq_init()
7021 (rb_bufsz << 1)); in cik_irq_init()
H A Devergreen.c3049 u32 rb_bufsz; in evergreen_cp_resume() local
3065 rb_bufsz = order_base_2(ring->ring_size / 8); in evergreen_cp_resume()
3066 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in evergreen_cp_resume()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_ih.c68 u32 rb_bufsz; in amdgpu_ih_ring_init() local
72 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
73 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
H A Dcz_ih.c106 int rb_bufsz; in cz_ih_irq_init() local
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
H A Diceland_ih.c106 int rb_bufsz; in iceland_ih_irq_init() local
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
H A Dtonga_ih.c102 int rb_bufsz; in tonga_ih_irq_init() local
126 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in tonga_ih_irq_init()
128 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
H A Dvega10_ih.c90 int rb_bufsz; in vega10_ih_irq_init() local
111 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in vega10_ih_irq_init()
114 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in vega10_ih_irq_init()
H A Duvd_v5_0.c297 uint32_t rb_bufsz, tmp; in uvd_v5_0_start() local
394 rb_bufsz = order_base_2(ring->ring_size); in uvd_v5_0_start()
396 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v5_0_start()
H A Dsdma_v2_4.c408 u32 rb_bufsz; in sdma_v2_4_gfx_resume() local
432 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v2_4_gfx_resume()
434 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
H A Duvd_v6_0.c717 uint32_t rb_bufsz, tmp; in uvd_v6_0_start() local
826 rb_bufsz = order_base_2(ring->ring_size); in uvd_v6_0_start()
827 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v6_0_start()
H A Dsdma_v3_0.c644 u32 rb_bufsz; in sdma_v3_0_gfx_resume() local
671 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v3_0_gfx_resume()
673 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v3_0_gfx_resume()
H A Dvcn_v1_0.c621 uint32_t rb_bufsz, tmp; in vcn_v1_0_start() local
733 rb_bufsz = order_base_2(ring->ring_size); in vcn_v1_0_start()
734 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v1_0_start()
H A Dsdma_v4_0.c621 u32 rb_bufsz; in sdma_v4_0_gfx_resume() local
636 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v4_0_gfx_resume()
638 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v4_0_gfx_resume()
H A Duvd_v7_0.c935 uint32_t rb_bufsz, tmp; in uvd_v7_0_start() local
1063 rb_bufsz = order_base_2(ring->ring_size); in uvd_v7_0_start()
1064 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v7_0_start()
H A Dgfx_v9_0.c2456 u32 rb_bufsz; in gfx_v9_0_cp_gfx_resume() local
2467 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v9_0_cp_gfx_resume()
2468 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
2469 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v9_0_cp_gfx_resume()
H A Dgfx_v8_0.c4474 u32 rb_bufsz; in gfx_v8_0_cp_gfx_resume() local
4486 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v8_0_cp_gfx_resume()
4487 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
4488 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v8_0_cp_gfx_resume()