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Searched refs:reference_divider (Results 1 – 13 of 13) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Drv730_dpm.c53 u32 reference_divider, post_divider; in rv730_populate_sclk_value() local
62 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
70 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()
97 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv730_populate_sclk_value()
132 u32 post_divider, reference_divider; in rv730_populate_mclk_value() local
140 reference_divider = dividers.ref_div + 1; in rv730_populate_mclk_value()
173 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv730_populate_mclk_value()
H A Drv740_dpm.c133 u32 reference_divider; in rv740_populate_sclk_value() local
142 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
144 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
165 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv740_populate_sclk_value()
H A Drv770_dpm.c329 u32 post_divider, reference_divider, feedback_divider8; in rv770_calculate_fractional_mpll_feedback_divider() local
338 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
341 (8 * fyclk * reference_divider * post_divider) / reference_clock; in rv770_calculate_fractional_mpll_feedback_divider()
506 u32 reference_divider, post_divider; in rv770_populate_sclk_value() local
515 reference_divider = 1 + dividers.ref_div; in rv770_populate_sclk_value()
522 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()
548 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv770_populate_sclk_value()
H A Dni_dpm.c2011 u32 reference_divider; in ni_calculate_sclk_params() local
2020 reference_divider = 1 + dividers.ref_div; in ni_calculate_sclk_params()
2023 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()
2044 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ni_calculate_sclk_params()
H A Dsi_dpm.c4795 u32 reference_divider; in si_calculate_sclk_params() local
4804 reference_divider = 1 + dividers.ref_div; in si_calculate_sclk_params()
4806 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()
4827 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in si_calculate_sclk_params()
H A Dci_dpm.c3204 u32 reference_divider; in ci_calculate_sclk_params() local
3214 reference_divider = 1 + dividers.ref_div; in ci_calculate_sclk_params()
3227 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ci_calculate_sclk_params()
/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_clock_source.c227 pll_settings->reference_divider = ref_divider; in calc_fb_divider_checking_tolerance()
327 if (pll_settings->reference_divider) { in calculate_pixel_clock_pll_dividers()
328 min_ref_divider = pll_settings->reference_divider; in calculate_pixel_clock_pll_dividers()
329 max_ref_divider = pll_settings->reference_divider; in calculate_pixel_clock_pll_dividers()
442 pll_settings->reference_divider = in pll_adjust_pix_clk()
443 bp_adjust_pixel_clock_params.reference_divider; in pll_adjust_pix_clk()
759 pll_settings->reference_divider * ss_data->modulation_freq_hz); in calculate_ss()
949 bp_pc_params.reference_divider = pll_settings->reference_divider; in dce110_program_pix_clk()
/dragonfly/sys/dev/drm/amd/display/include/
H A Dbios_parser_types.h199 uint32_t reference_divider; member
216 uint32_t reference_divider; member
/dragonfly/sys/dev/drm/amd/display/dc/inc/
H A Dclock_source.h112 uint32_t reference_divider; member
/dragonfly/sys/dev/drm/amd/display/dc/bios/
H A Dcommand_table.c959 cpu_to_le16((uint16_t)bp_params->reference_divider); in set_pixel_clock_v3()
1030 (uint8_t)(bp_params->reference_divider); in set_pixel_clock_v5()
1106 (uint8_t) bp_params->reference_divider; in set_pixel_clock_v6()
1523 bp_params->reference_divider = params.sOutput.ucRefDiv; in adjust_display_pll_v3()
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Diceland_smumgr.c806 uint32_t reference_divider; in iceland_calculate_sclk_params() local
819 reference_divider = 1 + dividers.uc_pll_ref_div; in iceland_calculate_sclk_params()
849 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); in iceland_calculate_sclk_params()
H A Dtonga_smumgr.c539 uint32_t reference_divider; in tonga_calculate_sclk_params() local
552 reference_divider = 1 + dividers.uc_pll_ref_div; in tonga_calculate_sclk_params()
582 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); in tonga_calculate_sclk_params()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsi_dpm.c5258 u32 reference_divider; in si_calculate_sclk_params() local
5267 reference_divider = 1 + dividers.ref_div; in si_calculate_sclk_params()
5269 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()
5290 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in si_calculate_sclk_params()